Mixed Signal Design/Verification Engineer
- Limerick
- Permanent
- Full-time
- UVM based Design Verification of Digital & Mixed-Signal IP Blocks
- Work closely with analog and digital design teams to verify RTL and Analog/Mixed-Signal IP blocks in a system level verification environment.
- Interact with architecture, design, physical design, software, design evaluation and test teams to design suitable verification and DFT strategies.
- Bachelor’s degree in electronic engineering or related field.
- Solid understanding of basics of analog and digital design, able to describe circuit behavior and functionality
- Experience in simulating circuits in spice simulators, debugging schematics, plotting and analyzing waveforms
- Demonstrated ability to read and write code in Verilog or System Verilog , use of digital simulators for verifying simple designs
- Work experience with mixed-signal test benches, SVA, functional coverage, constrained randomization and UPF
- Knowledge of any HDL for modeling such as Verilog-AMS; SV-RNM is highly desirable, UVM knowledge is a plus
- Experience of pre and post-silicon verification testflow and automated test benches. Post silicon ATE/PTE vector bringup and bench characterization support.
- Knowledge of test-plan development, coverage (code/functional) analysis, transaction level modelling, constrained random verification, assertion based and formal verification techniques with System Verilog
- Experience with Verilog, System Verilog, Assertions, Python/TCL/Perl/shell-scripting.
- Experience in analog mixed signal verification techniques will be a plus.
- Excellent communication skills
- Bachelor’s degree in science, Engineering, or related field.
- 3+ years design verification, or related work experience.