Sr Principal Design Engineer
Cadence Design Systems
- Cork
- Permanent
- Full-time
- Technical leadership of complex IP such as Ethernet, Storage, PCIe/CXL, MIPI-Visual
- Hands-on leadership of RTL, Testbenches & FPGA Platforms development
- Planning of activities and milestones for the Digital Controller Development teams
- Leadership of cross-functional technical meetings with Analog & Software counterparts
- Support customer pre-sales and post-sales meetings
- Participate in Technical Review Meetings and Checklist Reviews as part of ISO-9001
- Represent Cadence in Standards Body Working Groups e.g. IEEE, PCI-SIG, JEDEC, MIPI
- Represent Cadence by presenting at Industry Conference such as IEEE, DAC, MIPI Alliance
- Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
- 10-15 years’ experience in microelectronics/EDA industry
- Experience of Verilog RTL Design essential
- Experience of Metric Driven Verification (MDV) essential
- Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential
- Experience of SoC Architecture and Development essential
- Experience of Technical Team leadership essential
- Excellent oral and written English essential
- Self-motivated with excellent planning, interpersonal, and communication skills
- Experience of AMBA protocols such as AXI, AHB & APB preferred
- Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred
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