ASIC Digital Design, Sr Engineer
Synopsys
- Dublin
- Permanent
- Full-time
- Write verification plans and specifications
- Make architecture decisions on test bench design
- Implement test bench infrastructure and write test cases
- Implement a coverage driven methodology
- Perform a technical lead role
- BS/MS degree with a minimum of 2 years of related experience.
- Proficient in UVM.
- Programming skills such as C, System Verilog, TCL Perl or Python.
- Object oriented coding and verification solutions for productivity, performance, and throughput
- Experience of techniques such as assertion verification, coverage analysis and System Verilog for protocol-oriented performance analysis and debug
- The ability to work independently, precisely and to drive innovation
- Good communication skills.