Proficiency in one or more areas of CPU architecture: fetch, decode, branch prediction, renaming, execute units, SIMD, load/store, MMU, caches, retire, etc. Understanding of both the RISC-V ISA and our core and subsystem microarchitecture Work with design team and performance team to develop test case and validate new features Analyze and verify performance characteristics at multiple levels of simulation and emulation Writing performance analysis tools Running benchmarks and workloads under different conditions MS degree in Computer Engineering or Electrical Engineering 0-15 years of experience Good CPU architecture knowledge and micro-architecture knowledge Experience working in anRTL simulation environment Proficient in Verilog, C and C++ and scripting languages such as Perl or Python Ability to problem solve and prove your own ideas Knowledge and experience with common performance benchmarks and workloads Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field. References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
