Offer DescriptionJob Overview:The Cadence Serdes PHY team based at our R&D center of excellence in Cork, is seeking ambitious analog designers who wish to work on the leading edge of Wireline technology at the highest data rates (112Gbps+) and on the smallest technology nodes (e.g. 3nm ).The PHY team designs products for communication protocols such as PCIe (now at Gen 7) and UCIe (emerging Chiplets standard).The Senior Principal Analog Design Engineer will take a Technical Leadership role on the PMA design team as part of a SERDES Product Team.RequirementsAdditional InformationWebsite for additional job detailsWork Location(s)Number of offers available 1 Company/Institute Cadence EMEA Country Ireland City Cork GeofieldWhere to apply WebsiteContact CitySeveral locations in Germany, France, Italy, Israel, Sweden, UK WebsiteE-Mailwoodsb@cadence.comSTATUS: EXPIRED